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Macros</h2></td></tr>
<tr class="memitem:gafcbfb5805f763b09fd93a283afa8a55e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axicdma__v4__0.html#gafcbfb5805f763b09fd93a283afa8a55e">XAxiCdma_ReadReg</a>(BaseAddress,  RegOffset)                      &#160;&#160;&#160;XAxiCdma_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="separator:gafcbfb5805f763b09fd93a283afa8a55e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6d4705f0ef363ca8d3dab00df58728f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axicdma__v4__0.html#gad6d4705f0ef363ca8d3dab00df58728f">XAxiCdma_WriteReg</a>(BaseAddress,  RegOffset,  Data)                &#160;&#160;&#160;XAxiCdma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="separator:gad6d4705f0ef363ca8d3dab00df58728f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor Alignment</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Maximum transfer length</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This is determined by hardware </p>
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<tr><td colspan="2"><div class="groupHeader">Register offset definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register accesses are 32-bit. </p>
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<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXICDMA_SR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register reports status of a DMA channel, including idle state, errors, and interrupts </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXICDMA_CR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for descriptor</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for interrupts</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by XAXICDMA_CR_OFFSET register and XAXICDMA_SR_OFFSET register </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and shift for delay counter and coalescing counter</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by XAXICDMA_CR_OFFSET register and XAXICDMA_SR_OFFSET register </p>
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<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor offsets</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The first 8 words are used by hardware.</p>
<p>Cache operations are required for words used by hardware to enforce data consistency. All words after the 8th word are for software use only. </p>
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<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXICDMA_BD_CTRL_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXICDMA_BD_STS_OFFSET register</div></td></tr>
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